How to Upload Bitstream to Spartan 6 With Ise

Is your revenue in danger and are yous experiencing loss of concern because you are not getting your electronic components? Unfortunately, you are in good company with lots of other users.

I had several conversations recently with FPGA-users that had their blueprint done on competitors' devices, like for example, the Spartan-6, and they are at present facing the situation of an immediate stop of delivery. No devices at all anymore and redesign-options which are leading to either very large devices being used, crave taking care about a kick-process of a processor or strength migration to a new tool. Fifty-fifty and so, y'all may simply buy yourself a few years of availability.

How nigh actually protecting your futurity and cull an FPGA which:

• Is low attempt in migration
• Is available with no-end-of-life exercise

This is the perfect fourth dimension to turn an absolute crisis into a chance and Microchip is available to help you to get running once again. Simply like with the users that I talked with, they are planned to exist back up and running in product within virtually half a year.

In this article I will bear witness you lot a determination-tree for choosing an appropriate Microchip FPGA, how to drift the existing design from a software-perspective and some important differences and commonalities between Spartan-6 and the selected Microchip FPGAs.

Migration Decision

The immediate question on any migration from my perspective is the evaluation on an "if yes", "what so" and "how". For Spartan-6 some paths within the devices are circulated, east.g. the weblog from Adam Taylor. Adam has a valid decision tree; however, it stays completely within the Spartan-6 devices which may seem "natural" just is limiting your options. Additionally, you volition either end up with FPGAs of either 100.000 or 200.000 logic cells (Artix®-7 100T, Artix®-7 200T) supported by ISE or Zynq®-SoCs where yous must handle the boot-process as an essential part of the FPGA bring-up. And at this step a major redesign from a design built around a omnibus-centered MHS-file to a block-diagram based approach is required.

 An alternating decision-tree that brings yous into a no-end-of-life world is the following:

I start with the decision-point where you are looking into moving towards Microchip. Depending on your feel and evolution-expertise a microcontroller may be appropriate, which may non accept been bachelor at the design-fourth dimension of the original project. Me existence an FPGA-person I will non dive into that topic.

The adjacent step is mainly determining the master architecture. Is your blueprint "larger" so you may get some additional benefit during the migration, however if yous immediately require a redesign as your product-line is down then the right branch is for you.

Ane common use-instance in FPGA-designs is the apply of soft processors, similar MicroBlaze. If your design contains one (or perhaps multiple) of these then yous accept the option of migrating to either a soft RISC-V or a soft ARM Cortex M1 for PolarFire® FPGA or to use the hardened quad-core RISC-V in PolarFire SoC. Yes, this is a significant lift in performance, and it is your choice if you want or require this lift.

For immediate "one:1" replacements the correct main branch is important. Also, here we have the decision point of the MicroBlaze as soft processor. If you practise not have that soft processor and so the path is towards Igloo2 devices with or without transceivers as your blueprint requires it. With an existing MicroBlaze yous tin can benefit from the hardened ARM® Cortex M3 present in the SmartFusion2 devices. Every bit boosted benefit of this processor cluster you lot also receive several hardened peripherals that traditionally you had to build in FPGA textile. So, you may be able to select a device with a smaller logic complexity and with that improve your system on ability-consumption and everything that comes with it.

What are examples of these peripherals?

• DDR retention controller
• SPI / I2C / UART / Timer (two each)
• CAN
• Watchdog Timer
• Ethernet
• DMA

Additionally, SmartFusion®2 and Igloo®ii devices characteristic embedded non-volatile retention (eNVM) of up to 512kB, depending on the device size.

Based on this conclusion-tree you accept an impression on which device-family to utilize. The next step is judging the effort of a port to that family. As virtually of my contempo conversations take centered around an immediate need, I will prove what some conversion steps are to use a SmartFusion2 SoC or Igloo2 FPGA.

Blueprint Migration ISE to Libero SoC

A dubiousness-less requirement of migrating from Spartan-6 to anything else, including Spartan-seven, is the tool-migration. Spartan-6 was and is ISE, Spartan-7 is Vivado®, Microchip FPGAs are Libero® SoC.

For Spartan-half-dozen ordinarily a free-of-charge ISE WebPack® version was used, for Libero SoC the equivalent free-of-charge version is a silver license. Libero SoC can be downloaded here:

https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-blueprint-tools/fpga/libero-software-later-versions

The gratis of accuse license can be requested here:

https://www.microchip.com/en-the states/products/fpgas-and-plds/fpga-and-soc-design-tools/fpga/licensing

The adept news is, Libero SoC is non too different from ISE, you will easily find your way around:

The images to a higher place show the same design loaded into ISE and Libero SoC. Both tools accept projection management capabilities for implementation and simulation. The screenshots show the hierarchy of the design and allows navigation in the pattern. Additionally, the pattern-menses is also attainable from these GUIs, taking the designs from VHDL/Verilog® with IPs and constraints to the bitstream for the FPGA.

Equally Spartan-vi users may not be entirely familiar with Libero SoC as a tool my colleague Miguel Idiago and I take created a Python-script that converts from ane tool to the other. This script takes an ISE *.xise-file and creates a TCL-script for setting up a project with your sources in Libero SoC.  The conversion script is available upon request. The intent is to help with the initial steps of bringing something to live and take a first setup, notwithstanding this is non meant to exist a total conversion. A conscious limitation of the conversion-script is that merely HDL-sources are transferred. IP-components are of different format and need to be handled on an individual ground, the same applies for constraints.

When you run the script, you will likewise run into that not only IP-components are missing simply also base-components as the instantiations of the Unisim®-library similar Digital Clock Managers (DCMs), global clock-buffers (BUFG) or like.

For clocking the required rework is pretty straight frontward. One tin often simply supervene upon the component instantiation of BUFGs past a CLKINT-component. To get the correct architectural macros, their instantiations and port-maps please refer to the Macro Library User Guide:

• SmartFusion2 / IGLOO2: https://www.microsemi.com/document-portal/doc_download/130906-smartfusion2-and-igloo2-macro-library-guide
• PolarFire: https://www.microsemi.com/document-portal/doc_download/1245849-polarfire-macro-library-guide-for-libero-soc-v2021-2

To use the Digital Clock Manager or PLL of Spartan-vi you typically had some IP-instantiation created using a GUI for setting the appropriate features in ISE:

For Libero SoC the arroyo is similar, one tin can select an IP for the Clock Conditioning Circuit from the catalog-window:

In both cases the user is guided through the GUI to enter the pattern-requirements. Based on that the base-components are configured and show the closest possible matches. When all configurations are washed then IP-components and HDL-instantiations are created for instantiation in the overall design.

Constraints

Libero SoC uses SDC-based constraints and allows both a text- and GUI-based approach for creating these. The image below shows the GUI of the Constraints Editor which is used to build the SDC-commands for entering the clock-constraints but also for false paths or multicycle-constraints.

Using this GUI yous can filter your design-components to select the appropriate clock- or enable-sources and with that fix the timing.

For IO-constraints similar GUIs be that let drag- and drib assignment of individual ports or of complete interfaces as for DDR-memories. This makes using Microchip FPGAs very directly forward.

For those of the readers that prefer a script-based arroyo on their design for exact reproduction of design-runs, the design-flow in Libero SoC is completely scriptable.

Embedded Processing

The common embedded processor in Spartan-6 is the MicroBlaze soft-processor, implemented using FPGA-textile, frequently running at clock-frequencies between 66 MHz and 100 MHz. As SmartFusion2 SoCs already contain a microcontroller sub-organization (MSS) the suggested way of converting a MicroBlaze is to use this MSS with its ARM Cortex M3.

To port from MicroBlaze to M3 a transmission setup of the MSS is required. The Charabanc-Interface view of the Xilinx Platform Studio aids on this:

In this view one tin can encounter the various components and their connection. In Libero SoC 1 but needs to configure the MSS with its existing peripherals using a SmartDesign block:

The bachelor peripherals are office of the hardened MSS and hence no address-setup is required. Selecting or deselecting a peripheral is performed via the little tick-box on the bottom correct of each function-block. Next to this tick-box you have an additional icon for setting up properties of the IPs and whether they are routed out of the device via the defended MSS-IOs or via FPGA-material.

This SmartDesign cake with its MSS-configuration can be used either on a cake-based SmartDesign or be instantiated into an HDL-design. Depending on your original pattern you may prefer i or the other option.

Of import differences

The master difference between a Spartan-half dozen and a Microchip FPGA is the handling of the bitstream. Microchip-FPGAs have the programming-information of their agile components directly stored in Flash-cells and hence exercise non require a configuration at each power-cycle. Based on this, an external SPI-flash may not be required anymore.

With the benefits of the Flash-process some side-effects are introduced which may influence designs:

• Flipflops in Microchip FPGAs crave a reset at power-up for a defined country. Potential INIT-values based on indicate-declarations in the HDL cannot exist used for implementation and the synthesis-tool will upshot an appropriate alert. Designs without reset are discouraged.
• LSRAMs in SmartFusion2 and Igloo2 cannot be initialized at power-upward but need to exist loaded if to be used equally ROM. AC392 (https://www.microsemi.com/document-portal/doc_download/129978-ac392-smartfusion2-soc-fpga-sram-initialization-from-envm-libero-soc-v11-7-application-annotation) contains examples how this can exist achieved using the eNVM as storage for initialization-data and how to load the LSRAMs either via the M3 or cloth logic.
• Spartan-6 IOs are all capable of three.3V operation where SmartFusion2 and Igloo2 have a combination of IOs ranging up to 3.3V and up to 2.5V for higher functioning on lower power. If you are using lots of iii.3V IOs yous may need to put some extra consideration into your new package. This table gives an overview of the number of three.3V and 2.5V IOs in the various device- and package combinations:

Supporting 3.3V on 2.5 Volt inputs for Igloo2/SmartFusion2 can be achieved in the following way, documented in UG0445:

https://www.microsemi.com/certificate-portal/doc_download/132008-ug0445-smartfusion2-soc-fpga-and-igloo2-fpga-material-user-guide

UG0445 in chapter half-dozen.12 gives suggestions on resistors and their influence on the maximum data-rate usable with them.

The resistors work both equally a voltage-divider and a current limiter into the IO.

No End of Life

Microchip has an established and proven no-end-of-life practice, our FPGAs are not obsoleted. This allows you to confidently look into the futurity with communicated and supported availabilities of SmartFusion2 and Igloo2 devices of at least 15 years from today and for at least xx years for PolarFire. This bold statement is proven by history, devices that were introduced at the finish of the concluding millennium are all the same available for buy today.

Going for Microchip FPGAs will provide you lot with long term conviction and ease concerns about device-obsolescence.

Summary

Moving from Spartan-6 to Microchip FPGAs, specially SmartFusion2 and Igloo2 is direct forward and possible with reasonable effort. In instance conversion support is required then multiple levels are possible ranging from turn-central conversion from Microchip Design Services or Design Partner to simple conversations of what is the correct device to select.

Kickoff your hereafter today!

meyercoldingaze.blogspot.com

Source: https://www.linkedin.com/pulse/protect-your-future-microchip-fpga-device-place-martin-kellermann/

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